LLM inference
vLLM Architecture Lab
High-throughput LLM inference — PagedAttention, batching, KV cache.
Educational vLLM reference: PagedAttention, continuous batching, KV budgets, multi-LoRA economics — pairs with DomainForge adapter training (ADR-022).
In one sentence
Interactive vLLM architecture explorer — PagedAttention, batching, KV budget, adapter chat.
Decision
Educational simulator before GPU spend — teams learn inference architecture without H100 budget.
Measured signal
Live simulator · KV budget calculator · DomainForge↔vLLM Path B (ADR-022 Accepted).
Honest limitation
Simulator + educational adapter swap — not CUDA multi-LoRA kernels or production SLAs.
- PagedAttention block allocator with swap and prefix sharing
- FCFS scheduler — waiting / running / swapped queues
- KV memory budget calculator (H100 + Llama-3)
- Live API on Render · architecture explorer on Vercel
- Educational multi-LoRA Path B — `/v1/chat/completions` + `/v1/adapters`
Architecture diagram
Python · FastAPI · Vercel · Render